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general description the ds3904/ds3905 contain three nonvolatile (nv) low temperature coefficient, variable digital resistors. each resistor has 128 user-selectable positions. additionally, the ds3904/ds3905 have a high-impedance setting that allows each resistor to function as a digital switch. the ds3904/ds3905 can operate over a 2.7v to 5.5v supply voltage range, and communication with the device is achieved through a 2-wire serial interface. address pins allow multiple ds3904/ds3905s to operate on the same two-wire bus. the ds3904 has one address pin, allow- ing two ds3904s to share the bus, while the ds3905 has three address pins, allowing up to eight ds3905s to share a common bus. the low-cost and small size of the ds3904/ds3905 make them ideal replacements for con- ventional mechanical trimming resistors. applications power-supply calibration cell phones and pdas fibre optic transceiver modules portable electronics small and low-cost replacement for conventional mechanical trimming resistors/ dip switches test equipment features ? three 20k , or two 20k and one 10k , 128- position linear digital resistors ? resistor settings are stored in nv memory ? each resistor has a high-impedance setting for switch operation to control digital logic ? low temperature coefficient ? 2-wire serial interface ? 2.7v to 5.5v operating range ? -40c to +85c industrial temperature ? packaging: 8-pin sop for ds3904, 10-pin sop for ds3905 ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch _____________________________________________ maxim integrated products 1 pin configurations 0.1 f 4.7k 2-wire master v cc v cc h0 h1 h2 rhiz r 10 v cc scl sda (ds3905 only) a1 a2 resistor 0 addr f8h resistor 1 addr f9h resistor 2 addr fah a0 gnd 4.7k variable resistance for adjustable current source interface examples 2-wire addressable switch (using 00h and rhiz settings) gain control v in ds3904/ds3905 v cc rhiz rhiz r 11 digital logic r 12 typical operating circuit ordering information rev 3; 3/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package (r0/r1/r2) resistance (k ) ds3904u-010 -40c to +85c 8 sop 20/10/20 + high-z ds3904u-020 -40c to +85c 8 sop 20/20/20 + high-z DS3905U-020 -40c to +85c 10 sop 20/20/20 + high-z 8 6 5 1 3 4 sda top veiw a0 7 2 scl h0 h1 h2 sop v cc gnd ds3904 10 1 a1 a2 9 2 sda a0 sop 8 3h0 sdl 7 4 h1 v cc 6 5 h2 gnd ds3905
ds3904/ds3905 triple 128-position nonvolatile variable digital resistor/switch 2 ______________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +85?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc pin relative to ground.................-0.5v to +6.0v voltage on sda, scl, a0, a1, a2 relative to ground*...................................-0.5v to v cc + 0.5v voltage on h0, h1, and h2 relative to ground .......................................-0.5v to +6.0v current through h0, h1, and h2..........................................3ma operating temperature range ...........................-40 c to +85 c programming temperature range .........................0 c to +70 c storage temperature range .............................-55 c to +125 c soldering temperature...................see j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 5.5 v input logic 1 v ih 0.7 x v cc v cc + 0.3 v input logic 0 v il -0.3 0.3 x v cc v resistor current i r 3ma resistor terminals h0, h1, h2 v cc = +2.7v to +5.5v -0.3 +5.5 v dc electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?, unless otherwise noted.) parameter symbol conditions min typ max units input leakage i l (note 2) -1 +1 ? v cc = 3v (note 3) 95 200 standby supply current i stby v cc = 5v (note 3) 145 200 ? v ol1 3ma sink current 0 0.4 low-level output voltage (sda) v ol2 6ma sink current 0 0.6 v analog resistor characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?, unless otherwise noted.) parameter symbol conditions min typ max units 20k resistor -1 +1 absolute linearity (note 4) inl 10k resistor -1 +1 lsb 20k resistor -0.5 +0.5 relative linearity (note 5) dnl 10k resistor -0.5 +0.5 lsb position 7fh (20k resistor) -200 +123 +400 temperature coefficient (note 6) position 7fh (10k resistor) -150 +173 +450 ppm/c *this voltage must not exceed 6.0v.
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch _____________________________________________________________________ 3 ac electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units fast mode 0 400 scl clock frequency (note 7) f scl standard mode 0 100 khz fast mode 1.3 bus free time between stop and start conditions (note 7) t buf standard mode 4.7 ? fast mode 0.6 hold time (repeated) start condition (notes 7, 8) t hd:sta standard mode 4.0 ? fast mode 1.3 low period of scl clock (note 7) t low standard mode 4.7 ? fast mode 0.6 high period of scl clock (note 7) t high standard mode 4.0 ? fast mode 0 0.9 data hold time (notes 7, 9) t hd:dat standard mode 0 0.9 ? fast mode 100 data setup time (note 7) t su:dat standard mode 250 ns fast mode 0.6 start setup time t su:sta standard mode 4.7 ? fast mode 20 + 0.1c b 300 rise time of both sda and scl signals (note 10) t r standard mode 20 + 0.1c b 1000 ns fast mode 20 + 0.1c b 300 fall time of both sda and scl signals (note 10) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 ? capacitive load for each bus line c b (note 10) 400 pf eeprom write time t w (note 11) 10 20 ms startup time t st 2ms analog resistor characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +85?, unless otherwise noted.) parameter symbol conditions min typ max units t a = +25c (20k resistor) 14.5 20 25.5 position 7fh resistance r max t a = +25c (10k resistor) 8 10 12 k position 00h resistance r min t a = +25c 200 500 high impedance r hiz 5.5 m
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch 4 ______________________________________________________________________ note 1: all voltages are referenced to ground. note 2: applies to a0, sda, scl for the ds3904 and a0, a1, a2, sda, scl for the ds3905. also applies to h0, h1, h2 for both ds3904 and ds3905 when in the high-impedance state. note 3: i stby specified with sda = scl = v cc and a0 = gnd. note 4: absolute linearity is used to determine expected resistance. absolute linearity is defined as the deviation from the straight line drawn from the value of the resistance at position 00h to the value of the resistance at position 7fh. note 5: relative linearity is used to determine the change of resistance between two adjacent resistor positions. note 6: temperature coefficient specifies the change in resistance as a function of temperature. the temperature coefficient varies with resistor position. limits are guaranteed by design. note 7: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000ns + 250ns =1250ns before the scl line is released. note 8: after this period, the first clock pulse is generated. note 9: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 10: c b ?otal capacitance of one bus line in picofarads, timing referenced to 0.9 x v cc and 0.1 x v cc . note 11: eeprom write begins after a stop condition occurs. nonvolatile memory characteristics (v cc = +2.7v to +5.5v, t a = +70?.) parameter symbol conditions min typ max units eeprom writes 50,000
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch _____________________________________________________________________ 5 typical operating characteristics (v cc = +5.0v, t a = +25?, unless otherwise noted.) supply current vs. temperature ds3904/5 toc01 temperature ( c) supply current ( a) 60 40 -20 0 20 20 40 60 80 100 120 140 160 0 -40 80 v cc = +5v v cc = +3v sda = scl =v cc address pins connected to gnd supply current vs. scl frequency ds3904/5 toc02 scl frequency (khz) supply current ( a) 350 300 200 250 100 150 50 20 40 60 80 100 120 140 160 180 200 0 0 400 v cc = sda = +5v address pins connected to gnd resistance vs. resistor setting ds3904/5 toc03 resistor setting (dec) resistance (k ) 125 100 75 50 25 5 10 15 20 25 0 0 20k resistor 10k resistor temperature coefficient vs. resistor setting ds3904/5 toc04 resistor setting (dec) temperature coefficient (ppm/ c) 120 100 20 40 60 80 -100 0 100 200 300 400 500 600 -200 0 tc of +25 c to +85 c tc of +25 c to -40 c 20k resistor temperature coefficient vs. resistor setting ds3904/5 toc05 resistor setting (dec) temperature coefficient (ppm/ c) 120 100 60 80 40 20 100 200 300 400 500 600 700 800 900 0 0 tc of +25 c to +85 c tc of +25 c to -40 c 10k resistor position 7fh resistance percent change from +25 c vs. temperature ds3904/5 toc06 temperature ( c) resistance % change (from +25 c) 80 60 40 20 0 -20 -0.2 0 0.2 0.4 0.6 0.8 1.0 -0.4 -40 20k resistor 10k resistor position 00h resistance percent change from +25 c vs. temperature ds3904/5 toc07 temperature ( c) resistance % change (from +25 c) 80 60 20 40 0 -20 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -2.5 -40 20k resistor 10k resistor resistance vs. power-up voltage ds3904/5 toc08 power-up voltage (v) resistance (k ) 5 4 3 2 1 10 20 30 40 50 60 70 80 90 100 0 06 eeprom recall >5.5m programmed resistance resistance vs. power-down voltage ds3904/5 toc09 power-down voltage (v) resistance (k ) 5 4 3 2 1 10 20 30 40 50 60 70 80 90 100 0 06 eeprom recall programmed resistance >5.5m
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch 6 ______________________________________________________________________ typical operating characteristics (continued) (v cc = +5.0v, t a = +25?, unless otherwise noted.) position 3fh resistance vs. supply voltage ds3904/5 toc10 supply voltage (v) position 3fh resistance (k ) 5.5 5.0 4.5 4.0 3.5 3.0 5 10 15 20 25 0 2.5 6.0 10k resistor 20k resistor absolute linearity vs. resistor 0 position ds3904/5 toc11 resistor 0 position (dec) absolute linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 0 20k relative linearity vs. resistor 0 position ds3904/5 toc12 resistor 0 position (dec) relative linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 0 20k absolute linearity vs. resistor 1 position ds3904/5 toc13 resistor 1 position (dec) absolute linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 1 20k relative linearity vs. resistor 1 position ds3904/5 toc14 resistor 1 position (dec) relative linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 1 20k absolute linearity vs. resistor 2 position ds3904/5 toc15 resistor 2 position (dec) absolute linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 2 20k relative linearity vs. resistor 2 position ds3904/5 toc16 resistor 2 position (dec) relative linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 2 20k absolute linearity vs. resistor 1 position ds3904/5 toc17 resistor 1 position (dec) absolute linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 1 10k relative linearity vs. resistor 1 position ds3904/5 toc18 resistor 1 position (dec) relative linearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 resistor 1 10k
ds3904/ds3905 detailed description the ds3904/ds3905 contain three, 128-position, nv, low temperature coefficient, variable digital resistors. all three resistors also feature a hi-z function. the variable resistor registers (f8h, f9h, and fah) are factory pro- grammed with a default value of 7fh. they are con- trolled through a 2-wire serial interface, and can serve as a low-cost replacement for designs using conven- tional trimming resistors. furthermore, the ds3904 address pin (a0) allows two ds3904s to be placed on the same 2-wire bus. the three address pins on the ds3905 allow up to eight ds3905s to be placed on the same 2-wire bus. with their low cost and small size, the ds3904/ds3905 are well tailored to replace larger mechanical trimming variable resistors. this allows the automation of calibra- tion in many instances because the 2-wire interface can easily be adjusted by test/production equipment. variable resistor memory organization the variable resistors of the ds3904/ds3905 are addressed by communicating with the registers in table 1. using the resistor as a switch by taking advantage of the high-impedance mode, a switch can be created to produce a digital output. setting a resistor register to 00h creates the low state. writing 80h into the same resistor register enables the high-impedance state. when used with an external pullup resistor, such as a 4.7k pullup, a high state is generated. device operation clock and data transitions the sda pin is normally pulled high with an external resistor or device. data on the sda pin can only change during scl low time periods. data changes during scl high periods indicate a start or stop condition depend- ing on the conditions discussed below. see the timing diagrams for further details (figures 2 and 3). start condition a high-to-low transition of sda with scl high is a start condition, which must precede any other command. see the timing diagrams for further details (figures 2 and 3). stop condition a low-to-high transition of sda with scl high is a stop condition. after a read or write sequence, the stop com- mand places the ds3904/ds3905 into a low-power mode. see the timing diagrams for further details (figures 2 and 3). acknowledge all address and data bytes are transmitted through a serial protocol. the ds3904/ds3905 pull the sda line low during the ninth clock pulse to acknowledge that they have received each byte. standby mode the ds3904/ds3905 feature a low-power mode that is automatically enabled after power-on, after a stop com- mand, and after the completion of all internal operations. pin description pin name ds3904 ds3905 description sda 1 2 2-wire serial data. open-drain input/output for 2-wire data. scl 2 3 2-wire serial clock. input for 2-wire clock. v cc 3 4 supply voltage terminal gnd 4 5 ground terminal h2 5 6 resistor 2 high terminals h1 6 7 resistor 1 high terminals h0 7 8 resistor 0 high terminals a0 8 9 address-select pin a1 1 ad d r ess- s el ect p i n ( d s 3905 onl y) a2 10 ad d r ess- s el ect p i n ( d s 3905 onl y) triple 128-position nonvolatile digital variable resistor/switch _____________________________________________________________________ 7 table 1. variable resistor registers address variable resistor position 7fh resistance number of positions* f8h resistor 0 20k (nominal) 128 (00h to 7fh) + hi-z f9h resistor 1 20k or 10k (nominal) 128 (00h to 7fh) + hi-z fah resistor 2 20k (nominal) 128 (00h to 7fh) + hi-z * writing a value greater than 7fh to any of the resistor registers sets the high-impedance mode control bit (rhiz, the msb of the resistor register) resulting in the resistor going into high- impedance mode. position 0 is the minimum position. position 7fh is the maximum position.
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch 8 ______________________________________________________________________ bus reset after any interruption in protocol, power loss, or system reset, the following steps reset the ds3904/ds3905: 1) clock up to nine cycles. 2) look for sda high in each cycle while scl is high. 3) create a start condition while sda is high. device addressing the ds3904/ds3905 must receive an 8-bit device address byte following a start condition to enable a specific device for a read or write operation. the address byte is clocked into the ds3904/ds3905 msb to lsb. for the ds3904, the address byte consists of 101000 binary followed by a0 then the r/ w bit. if the r/ w bit is high, a read operation is initiated. for the ds3905, the address byte consists of 1010 binary fol- lowed by a2, a1, a0 then the r/ w bit. if the r/ w bit is low, a write operation is initiated. for a device to become active, the value of the address bits must be the same as the hard-wired address pins on the ds3904/ds3905. upon a match of written and hard- wired addresses, the ds3904/ds3905 output a zero for one clock cycle as an acknowledge. if the address does not match, the ds3904/ds3905 return to a low- power mode. write operations after receiving a matching device address byte with the r/ w bit set low, the device goes into the write mode of operation. the master must transmit an 8-bit eeprom memory address to the device to define the address where the data is to be written. after the byte has been received, the ds3904/ds3905 transmit a zero for one clock cycle to acknowledge that the memory address has been received. the master must then transmit an 8- bit data word to be written into this memory address. the ds3904/ds3905 again transmit a zero for one clock cycle to acknowledge the receipt of the data byte. at this point, the master must terminate the write operation with a stop condition. the ds3904/ds3905 then enter an internally timed write process t w to the eeprom memo- ry. all inputs are disabled during this write cycle. acknowledge polling once a eeprom write is initiated, the part will not acknowledge until the cycle is complete. another option is to wait the maximum write cycle delay before initiating another write cycle. read operations after receiving a matching address byte with the r/ w bit set high, the device goes into the read mode of opera- tion. a read requires a dummy byte write sequence to load in the register address. once the device address and data address bytes are clocked in by the master, and acknowledged by the ds3904/ ds3905, the master must generate another start condition (repeated start). the master now initiates a read by sending the device address with the r/ w bit set high. the ds3904/ds3905 acknowledge the device address and serially clock out the data byte. the master responds with a nack and generates a stop condition afterwards. see figures 4 and 5 for command and data byte struc- tures as well as read and write examples. 2-wire serial port operation the 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. a device that sends data on the bus is defined as a trans- mitter, and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that gener- ates the scl, controls the bus access, and generates the start and stop conditions. the ds3904/ds3905 oper- ate as slaves on the 2-wire bus. connections to the bus are made through scl and open-drain sda lines. the following i/o terminals control the 2-wire serial port: sda, scl, and a0. the ds3905 uses two additional address pins a1 and a2 to control the 2-wire serial port. timing diagrams for the 2-wire serial port can be found in figures 2 and 3. timing information for the 2-wire serial port is provided in the ac electrical characteristics table for 2-wire serial communications. 2-wire interface rhiz control eeprom res 0 20k h0 f8h msb 7 lsb data gnd scl sda a0 v cc v cc ds3905 resistor 0 rhiz control res 1 20k or 10k h1 f9h msb lsb resistor 1 rhiz control res 2 20k h2 fah msb lsb resistor 2 7 7 (ds3905 only) a1 a2 figure 1. ds3904/ds3905 block diagram
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch _____________________________________________________________________ 9 the following bus protocol has been defined: data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain sta- ble whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line can be changed during the low period of the clock signal. there is stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 2. 2-wire data transfer protocol sda scl t hd:sta t low t high t r t f t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start t buf figure 3. 2-wire ac characteristics
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch 10 _____________________________________________________________________ one clock pulse per bit of data. figures 2 and 3 detail how data transfer is accomplished on the 2- wire bus. depending upon the state of the r/ w bit, two types of data transfer are possible. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte- wise and each receiver acknowledges with a ninth bit. within the bus specifications, a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds3904/ds3905 work in both modes. acknowledge: each receiving device, when addressed, generates an acknowledge after the byte has been received. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowl- edge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data transfer from a slave transmitter to a mas- ter receiver. the master transmits the first byte (the command/control byte) to the slave. the slave then returns an acknowledge bit. next follows the data byte transmitted by the slave to the master. the master returns nack followed by a stop. the master device generates all serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. 1 msb start lsb command byte * ds3904, use 0's instead of a2 and a1 for the device address device identifier or "family code" slave address 0 1 0 a2* a1* a0 r/w msb lsb data byte rhiz control bit resistor setting figure 4. command and data byte structures msb a0h a0h a0h a0h a1h f8h f9h fah 00h 80h 7fh f9h lsb 10 0 10 00 start msb lsb 111 ack ack 11000 msb lsb 0 10 0 10 00 start msb lsb 111 ack stop ack 11001 msb lsb 0 10 0 10 00 start msb lsb 111 ack stop ack 11010 msb lsb 10 0 10 00 start msb lsb 111 ack ack 11001 read resistor 1 value a0 = gnd for ds3904 a0, a1, a2 = gnd for ds3905 write resistor 0 to min position msb lsb 10 0 10 00 repeated start msb lsb ack stop nack from slave from slave from slave master 0 0 1 stop msb lsb 000 ack 00000 msb lsb 100 ack 00000 msb lsb 011 ack 11111 set resistor 1 to hi-z write resistor 2 to max position example 2-wire transactions resistor data figure 5. example 2-wire transactions
ds3904/ds3905 triple 128-position nonvolatile digital variable resistor/switch maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. the ds3904/ds3905 can operate in the following three modes: 1) slave receiver mode: serial data and clock are received through sda and scl, respectively. after each byte is received, an acknowledge bit is trans- mitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after the slave (device) address and direction bit has been received. 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the ds3904/ds3905 while the serial clock is input on scl. start and stop con- ditions are recognized as the beginning and end of a serial transfer. 3) slave address: the command/control byte is the first byte received following the start condition from the master device. the command/control byte con- sists of a 4-bit device identifier. for the ds3904, the identifier is followed by the device-select bits 0, 0, and a0. for the ds3905, the identifier is followed by the device-select bits a2, a1, a0. the device identi- fier is used by the master device to select which device is to be accessed. when reading or writing the ds3904/ds3905, the device-select bits must match the device-select pin(s). the last bit of the command/control byte (r/ w ) defines the operation to be performed. when set to a ?? a read operation is selected, and when set to a ?? a write operation is selected. following the start condition, the ds3904/ds3905 moni- tor the sda bus checking the device-type identifier being transmitted. upon receiving the control code, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the sda line. applications information power-supply decoupling to achieve the best results when using the ds3904/ ds3905, decouple the power supply with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface- mount capacitor. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-fre- quency response for decoupling applications. high resistor terminal voltage it is possible to have a voltage on the resistor-high termi- nals that is higher than the voltage connected to v cc . for instance, connecting v cc to 3.0v while one or more of the resistor high terminals are connected to 5.0v allows a 3v system to control a 5v system. the 5.5v maximum still applies to the limit on the resistor high ter- minals regardless of the voltage present on v cc . package information for the latest package outline information, go to www.maxim-ic. com/dallaspackinfo .

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